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Improve Debugging And Performance Tuning With ETW

March 3rd, 2010 플럿 No comments

Improve Debugging And Performance Tuning With ETW

http://msdn.microsoft.com/en-us/magazine/cc163437.aspx

활용해볼만한 가치가 있는 것.

Categories: Development Tags:

새로운 SSDT 후킹기법

May 7th, 2007 플럿 No comments

http://www.avertlabs.com/research/blog/?p=269

아직 읽어보진 않았지만…

Jeff 님께서 알려주신 내용~ 감사감사~ ^^

Categories: Development Tags: ,

NDSL S/W 개발?

April 23rd, 2007 플럿 No comments

NDSL 개발 관련 사이트 모음

Nintendo DS Technical Information
http://neimod.com/dstek/

개발툴:
http://www.devkitpro.org/

기타:
http://www.dev-scene.com/Main_Page

추가 사이트는.. 점점 늘어난당..

Categories: Development, IT Tags: ,

Ten Essential Tools – VS Add-ins

February 2nd, 2007 플럿 No comments

Ten Essential Tools
Visual Studio Add-ins every Developer Should Download Now.

당장 다운로드 받아야할 VS Add-ins!!!

내용을 보자~~

여기~~!

Categories: Development Tags:

Windows internals – Chapter3 #1

January 8th, 2007 플럿 No comments

[Trap Dispatching]

Interrupt Dispatching

Hardware Interrupt Processing
Software Interrupt Request Levels (IRQLs)

Software Interrupts
Dispatch or deferred procedure call (DPC) interrupts
Asynchronous procedure call (APC) interrupts

Exception Dispatching
System Service Dispatching

이게 바로 매트릭스여~

Categories: Development Tags:

Cypress CY7C68013

December 22nd, 2006 플럿 No comments

USB 공부를 위한.. 첫번째걸음

Cypress CY7C68013 칩 안내.
datasheet를 확인할 수 있다!

이건. CY7C68013A
EZ-USB FX2LP(TM) USB Microcontroller

Features

  • USB 2.0-USB-IF high speed certified (TID # 40440111)
  • Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor
  • Fit, form and function compatible with the FX2
    • Pin-compatible
    • Object-code-compatible
    • Functionally-compatible (FX2LP is a superset)
  • Ultra Low power: ICC no more than 85 mA in any mode
    • Ideal for bus and battery powered applications
  • Software: 8051 code runs from:
    • Internal RAM, which is downloaded via USB
    • Internal RAM, which is loaded from EEPROM
    • External memory device (128 pin package)
  • 16 KBytes of on-chip Code/Data RAM
  • Four programmable
  • BULK/INTERRUPT/ISOCHRONOUS endpoints
    • Buffering options: double, triple, and quad
  • Additional programmable (BULK/INTERRUPT) 64-byte endpoint
  • 8- or 16-bit external data interface
  • Smart Media Standard ECC generation
  • GPIF (General Programmable Interface)
    • Allows direct connection to most parallel interface
    • Programmable waveform descriptors and configuration registers to define waveforms
    • Supports multiple Ready (RDY) inputs and Control (CTL) outputs
  • Integrated, industry-standard enhanced 8051
    • 48-MHz, 24-MHz, or 12-MHz CPU operation
    • Four clocks per instruction cycle
    • Two USARTS
    • Three counter/timers
    • Expanded interrupt system
    • Two data pointers
  • 3.3V operation with 5V tolerant inputs
  • Vectored USB interrupts and GPIF/FIFO interrupts
  • Separate data buffers for the Set-up and Data portions of a CONTROL transfer
  • Integrated I2C controller, runs at 100 or 400 kHz
  • Four integrated FIFOs
    • Integrated glue logic and FIFOs lower system cost
    • Automatic conversion to and from 16-bit buses
    • Master or slave operation
    • Uses external clock or asynchronous strobes
    • Easy interface to ASIC and DSP ICs
  • Available in Commercial and Industrial temperature grade (all packages except VFBGA)
Categories: Development Tags: ,